In recent years, along with reductions in size and weight of mobile devices as typified by cellular phones and digital cameras, and information storage media as typified by memory cards, semiconductor chips embedded in these have been made thinner. For this reason, while a dicing process obtains individual thin semiconductor chips by cutting a thin semiconductor wafer, chipping tends to occur in the semiconductor chips due to their thinness in a dicing process using a blade dicing method, thereby causing a problem of significant decrease in bending strength of the thin semiconductor chips. Moreover, although a low-dielectric-constant film (so-called Low-k film) having a dielectric constant lower than that of silicon oxide is used for an insulating film between wiring layers of a semiconductor chip in view of improving an operation speed of a semiconductor device, such a Low-k film is brittle and tends to peel off, and may have subtle air bubbles therein, and therefore may not be able to be cut well through blade dicing.
To get around these problems, stealth dicing has attracted attentions as a new dicing method. In stealth dicing, the inside of a semiconductor wafer is radiated with laser beam to selectively form a modified layer, and the semiconductor wafer is cut with taking this modified layer as a division starting point. In this method, even an extremely thin semiconductor wafer having a thickness on the order of 30 μm can be directly cut off without physically applying stress, thereby reducing chipping and suppressing reduction in bending strength of the semiconductor chips. Also, regardless of the thickness of semiconductor wafers, high-speed dicing over 300 mm per second can be performed, thereby also increasing throughput. Therefore, for making semiconductor chips thinner, stealth dicing is an indispensable technology.
Such stealth dicing technology is described in, for example, Japanese Patent Application Laid-Open Publication No. 2004-221286 (Patent Document 1). In paragraph 0022 and FIG. 1 of this Patent Document 1, a structure is disclosed in which a wiring layer is provided on both sides of a test pad in a region between chips. These wiring layers are not for electrical coupling, but are dummy patterns for homogenizing a radiation region of laser beams and causing the laser beams to be easily absorbed. Further, in paragraph 0023 of this Patent Document 1, a method is disclosed in which a laser beam is irradiated to the region to melt for cutting the semiconductor wafer in dividing the semiconductor wafer. Furthermore, in paragraph 0024 of this Patent Document 1, a method is disclosed in which, a melting-processing region is formed through multiphoton absorption by placing a focal point of the laser beam at the inside of the semiconductor wafer, and then the semiconductor wafer is diced by cracking method or expansion method upon dividing the semiconductor wafer.
And, for example, in Japanese Patent Application Laid-Open Publication No. 2005-340426 (Patent Document 2), a stealth dicing technology is disclosed in which, after a groove is formed on a test bonding pad on a main surface of a semiconductor wafer, a tape is adhered on the main surface of the semiconductor wafer and a laser beam is irradiated from the back surface of the semiconductor wafer to form a modified layer inside of the semiconductor wafer, and then the tape is expanded to divide the semiconductor wafer into individual semiconductor chips with taking the modified layer as the starting point.
Still further, for example, in Japanese Patent Application Laid-Open Publication No. 2005-32903 (Patent Document 3), a stealth dicing technology is disclosed in which, after a test electrode pad and the like on a main surface of a semiconductor wafer is removed by a blade, a laser beam is radiated from the main surface of the semiconductor wafer to form a modified layer inside of the semiconductor wafer, and then a dicing tape is expanded to divide the semiconductor wafer into individual semiconductor chips with taking the modified layer as the starting point.
Patent document 1: Japanese Patent Laid-Open Publication No. 2004-221286, (paragraphs 0022-0024 and FIG. 1)
Patent document 2: Japanese Patent Laid-Open Publication No. 2005-340426
Patent document 3: Japanese Patent Laid-Open Publication No. 2005-32903